`timescale 1ns/1ps
`default_nettype none

module cxy_pixel_display_buf_2
    #(
    parameter   DW  = 96
    )
    (
    input  wire         I_sdram_clk,
    input  wire         I_rst_n,
    // write
    input  wire         I_buf_frm_start,
    input  wire         I_buf_sel,
    input  wire         I_buf_vld,
    input  wire [4:0]   I_buf_port,
    input  wire         I_buf_port_end,
    input  wire [23:0]  I_buf_data,
    // read
    input  wire         I_rclk,
    input  wire         I_rden,
    input  wire [9:0]   I_raddr,
    output wire [DW-1:0] O_rdata
    );
//***********************************************************
reg             reg_grp;

reg  [23:0]     g0_p0;
reg  [23:0]     g0_p1;
reg  [23:0]     g0_p2;
reg  [23:0]     g0_p3;
reg  [23:0]     g0_p4;
reg  [23:0]     g0_p5;
reg  [23:0]     g0_p6;
reg  [23:0]     g0_p7;
reg  [23:0]     g0_p8;
reg  [23:0]     g0_p9;
reg  [23:0]     g0_p10;
reg  [23:0]     g0_p11;
reg  [23:0]     g0_p12;
reg  [23:0]     g0_p13;
reg  [23:0]     g0_p14;
reg  [23:0]     g0_p15;
reg  [23:0]     g0_p16;
reg  [23:0]     g0_p17;
reg  [23:0]     g0_p18;
reg  [23:0]     g0_p19;
reg  [23:0]     g0_p20;
reg  [23:0]     g0_p21;
reg  [23:0]     g0_p22;
reg  [23:0]     g0_p23;
reg  [23:0]     g0_p24;
reg  [23:0]     g0_p25;
reg  [23:0]     g0_p26;
reg  [23:0]     g0_p27;
reg  [23:0]     g0_p28;
reg  [23:0]     g0_p29;
reg  [23:0]     g0_p30;
reg  [23:0]     g0_p31;

reg  [23:0]     g1_p0;
reg  [23:0]     g1_p1;
reg  [23:0]     g1_p2;
reg  [23:0]     g1_p3;
reg  [23:0]     g1_p4;
reg  [23:0]     g1_p5;
reg  [23:0]     g1_p6;
reg  [23:0]     g1_p7;
reg  [23:0]     g1_p8;
reg  [23:0]     g1_p9;
reg  [23:0]     g1_p10;
reg  [23:0]     g1_p11;
reg  [23:0]     g1_p12;
reg  [23:0]     g1_p13;
reg  [23:0]     g1_p14;
reg  [23:0]     g1_p15;
reg  [23:0]     g1_p16;
reg  [23:0]     g1_p17;
reg  [23:0]     g1_p18;
reg  [23:0]     g1_p19;
reg  [23:0]     g1_p20;
reg  [23:0]     g1_p21;
reg  [23:0]     g1_p22;
reg  [23:0]     g1_p23;
reg  [23:0]     g1_p24;
reg  [23:0]     g1_p25;
reg  [23:0]     g1_p26;
reg  [23:0]     g1_p27;
reg  [23:0]     g1_p28;
reg  [23:0]     g1_p29;
reg  [23:0]     g1_p30;
reg  [23:0]     g1_p31;

reg             wren;
reg  [1:0]      wr_cnt;
reg  [7:0]      waddr;

reg             ram_wren;
wire [8:0]      ram_waddr;
reg  [143:0]    ram_wdata;
//***********************************************************
//reg_grp
always@(posedge I_sdram_clk or negedge I_rst_n)
    if(!I_rst_n)
        reg_grp <= 'b0;
    else if(I_buf_frm_start)
        reg_grp <= 'b0;
    else if(I_buf_port_end)
        reg_grp <= ~reg_grp;

//gx_dx[23:0]
always@(posedge I_sdram_clk)
    if(I_buf_vld && reg_grp==0)
        case(I_buf_port)
            0 :     g0_p0  <= I_buf_data;
            1 :     g0_p1  <= I_buf_data;
            2 :     g0_p2  <= I_buf_data;
            3 :     g0_p3  <= I_buf_data;
            4 :     g0_p4  <= I_buf_data;
            5 :     g0_p5  <= I_buf_data;
            6 :     g0_p6  <= I_buf_data;
            7 :     g0_p7  <= I_buf_data;
            8 :     g0_p8  <= I_buf_data;
            9 :     g0_p9  <= I_buf_data;
            10:     g0_p10 <= I_buf_data;
            11:     g0_p11 <= I_buf_data;
            12:     g0_p12 <= I_buf_data;
            13:     g0_p13 <= I_buf_data;
            14:     g0_p14 <= I_buf_data;
            15:     g0_p15 <= I_buf_data;
            16:     g0_p16 <= I_buf_data;
            17:     g0_p17 <= I_buf_data;
            18:     g0_p18 <= I_buf_data;
            19:     g0_p19 <= I_buf_data;
            20:     g0_p20 <= I_buf_data;
            21:     g0_p21 <= I_buf_data;
            22:     g0_p22 <= I_buf_data;
            23:     g0_p23 <= I_buf_data;
            24:     g0_p24 <= I_buf_data;
            25:     g0_p25 <= I_buf_data;
            26:     g0_p26 <= I_buf_data;
            27:     g0_p27 <= I_buf_data;
            28:     g0_p28 <= I_buf_data;
            29:     g0_p29 <= I_buf_data;
            30:     g0_p30 <= I_buf_data;
            31:     g0_p31 <= I_buf_data;
        endcase
    else if(I_buf_vld && reg_grp==1)
        case(I_buf_port)
            0 :     g1_p0  <= I_buf_data;
            1 :     g1_p1  <= I_buf_data;
            2 :     g1_p2  <= I_buf_data;
            3 :     g1_p3  <= I_buf_data;
            4 :     g1_p4  <= I_buf_data;
            5 :     g1_p5  <= I_buf_data;
            6 :     g1_p6  <= I_buf_data;
            7 :     g1_p7  <= I_buf_data;
            8 :     g1_p8  <= I_buf_data;
            9 :     g1_p9  <= I_buf_data;
            10:     g1_p10 <= I_buf_data;
            11:     g1_p11 <= I_buf_data;
            12:     g1_p12 <= I_buf_data;
            13:     g1_p13 <= I_buf_data;
            14:     g1_p14 <= I_buf_data;
            15:     g1_p15 <= I_buf_data;
            16:     g1_p16 <= I_buf_data;
            17:     g1_p17 <= I_buf_data;
            18:     g1_p18 <= I_buf_data;
            19:     g1_p19 <= I_buf_data;
            20:     g1_p20 <= I_buf_data;
            21:     g1_p21 <= I_buf_data;
            22:     g1_p22 <= I_buf_data;
            23:     g1_p23 <= I_buf_data;
            24:     g1_p24 <= I_buf_data;
            25:     g1_p25 <= I_buf_data;
            26:     g1_p26 <= I_buf_data;
            27:     g1_p27 <= I_buf_data;
            28:     g1_p28 <= I_buf_data;
            29:     g1_p29 <= I_buf_data;
            30:     g1_p30 <= I_buf_data;
            31:     g1_p31 <= I_buf_data;
        endcase
//***********************************************************
//wren
always@(posedge I_sdram_clk or negedge I_rst_n)
    if(!I_rst_n)
        wren <= 'b0;
    else if(I_buf_port_end)
        wren <= 1'b1;
    else if(wr_cnt==3)
        wren <= 'b0;

//wr_cnt[1:0]
always@(posedge I_sdram_clk or negedge I_rst_n)
    if(!I_rst_n)
        wr_cnt <= 'b0;
    else if(wren)
        wr_cnt <= wr_cnt + 1'b1;
    else
        wr_cnt <= 'b0;

//ram_wren
always@(posedge I_sdram_clk or negedge I_rst_n)
    if(!I_rst_n)
        ram_wren <= 'b0;
    else
        ram_wren <= wren;

//waddr[7:0]
always@(posedge I_sdram_clk or negedge I_rst_n)
    if(!I_rst_n)
        waddr <= 'b0;
    else if(I_buf_frm_start)
        waddr <= 'b0;
    else if(ram_wren)
        waddr <= waddr + 1'b1;

//ram_waddr[8:0]
assign ram_waddr = {I_buf_sel,waddr};

//ram_wdata[143:0]
always@(posedge I_sdram_clk)
    if(wren && reg_grp==1)
        case(wr_cnt)
            0:      ram_wdata <= {
                                //g0_p31[5 :3 ],g0_p30[5 :3 ],g0_p29[5 :3 ],g0_p28[5 :3 ],g0_p27[5 :3 ],g0_p26[5 :3 ],g0_p25[5 :3 ],g0_p24[5 :3 ],
                                  g0_p23[5 :3 ],g0_p22[5 :3 ],g0_p21[5 :3 ],g0_p20[5 :3 ],g0_p19[5 :3 ],g0_p18[5 :3 ],g0_p17[5 :3 ],g0_p16[5 :3 ],
                                  g0_p15[5 :3 ],g0_p14[5 :3 ],g0_p13[5 :3 ],g0_p12[5 :3 ],g0_p11[5 :3 ],g0_p10[5 :3 ],g0_p9 [5 :3 ],g0_p8 [5 :3 ],
                                  g0_p7 [5 :3 ],g0_p6 [5 :3 ],g0_p5 [5 :3 ],g0_p4 [5 :3 ],g0_p3 [5 :3 ],g0_p2 [5 :3 ],g0_p1 [5 :3 ],g0_p0 [5 :3 ],

                                //g0_p31[2 :0 ],g0_p30[2 :0 ],g0_p29[2 :0 ],g0_p28[2 :0 ],g0_p27[2 :0 ],g0_p26[2 :0 ],g0_p25[2 :0 ],g0_p24[2 :0 ],
                                  g0_p23[2 :0 ],g0_p22[2 :0 ],g0_p21[2 :0 ],g0_p20[2 :0 ],g0_p19[2 :0 ],g0_p18[2 :0 ],g0_p17[2 :0 ],g0_p16[2 :0 ],
                                  g0_p15[2 :0 ],g0_p14[2 :0 ],g0_p13[2 :0 ],g0_p12[2 :0 ],g0_p11[2 :0 ],g0_p10[2 :0 ],g0_p9 [2 :0 ],g0_p8 [2 :0 ],
                                  g0_p7 [2 :0 ],g0_p6 [2 :0 ],g0_p5 [2 :0 ],g0_p4 [2 :0 ],g0_p3 [2 :0 ],g0_p2 [2 :0 ],g0_p1 [2 :0 ],g0_p0 [2 :0 ]};

            1:      ram_wdata <= {
                                //g0_p31[11:9 ],g0_p30[11:9 ],g0_p29[11:9 ],g0_p28[11:9 ],g0_p27[11:9 ],g0_p26[11:9 ],g0_p25[11:9 ],g0_p24[11:9 ],
                                  g0_p23[11:9 ],g0_p22[11:9 ],g0_p21[11:9 ],g0_p20[11:9 ],g0_p19[11:9 ],g0_p18[11:9 ],g0_p17[11:9 ],g0_p16[11:9 ],
                                  g0_p15[11:9 ],g0_p14[11:9 ],g0_p13[11:9 ],g0_p12[11:9 ],g0_p11[11:9 ],g0_p10[11:9 ],g0_p9 [11:9 ],g0_p8 [11:9 ],
                                  g0_p7 [11:9 ],g0_p6 [11:9 ],g0_p5 [11:9 ],g0_p4 [11:9 ],g0_p3 [11:9 ],g0_p2 [11:9 ],g0_p1 [11:9 ],g0_p0 [11:9 ],
                                                                                                                                                
                                //g0_p31[8 :6 ],g0_p30[8 :6 ],g0_p29[8 :6 ],g0_p28[8 :6 ],g0_p27[8 :6 ],g0_p26[8 :6 ],g0_p25[8 :6 ],g0_p24[8 :6 ],
                                  g0_p23[8 :6 ],g0_p22[8 :6 ],g0_p21[8 :6 ],g0_p20[8 :6 ],g0_p19[8 :6 ],g0_p18[8 :6 ],g0_p17[8 :6 ],g0_p16[8 :6 ],
                                  g0_p15[8 :6 ],g0_p14[8 :6 ],g0_p13[8 :6 ],g0_p12[8 :6 ],g0_p11[8 :6 ],g0_p10[8 :6 ],g0_p9 [8 :6 ],g0_p8 [8 :6 ],
                                  g0_p7 [8 :6 ],g0_p6 [8 :6 ],g0_p5 [8 :6 ],g0_p4 [8 :6 ],g0_p3 [8 :6 ],g0_p2 [8 :6 ],g0_p1 [8 :6 ],g0_p0 [8 :6 ]};
                                                                                                                                                
            2:      ram_wdata <= {
                                //g0_p31[17:15],g0_p30[17:15],g0_p29[17:15],g0_p28[17:15],g0_p27[17:15],g0_p26[17:15],g0_p25[17:15],g0_p24[17:15],
                                  g0_p23[17:15],g0_p22[17:15],g0_p21[17:15],g0_p20[17:15],g0_p19[17:15],g0_p18[17:15],g0_p17[17:15],g0_p16[17:15],
                                  g0_p15[17:15],g0_p14[17:15],g0_p13[17:15],g0_p12[17:15],g0_p11[17:15],g0_p10[17:15],g0_p9 [17:15],g0_p8 [17:15],
                                  g0_p7 [17:15],g0_p6 [17:15],g0_p5 [17:15],g0_p4 [17:15],g0_p3 [17:15],g0_p2 [17:15],g0_p1 [17:15],g0_p0 [17:15],
                                                                                                                                                
                                //g0_p31[14:12],g0_p30[14:12],g0_p29[14:12],g0_p28[14:12],g0_p27[14:12],g0_p26[14:12],g0_p25[14:12],g0_p24[14:12],
                                  g0_p23[14:12],g0_p22[14:12],g0_p21[14:12],g0_p20[14:12],g0_p19[14:12],g0_p18[14:12],g0_p17[14:12],g0_p16[14:12],
                                  g0_p15[14:12],g0_p14[14:12],g0_p13[14:12],g0_p12[14:12],g0_p11[14:12],g0_p10[14:12],g0_p9 [14:12],g0_p8 [14:12],
                                  g0_p7 [14:12],g0_p6 [14:12],g0_p5 [14:12],g0_p4 [14:12],g0_p3 [14:12],g0_p2 [14:12],g0_p1 [14:12],g0_p0 [14:12]};
                                                                                                                                                
            3:      ram_wdata <= {
                                //g0_p31[23:21],g0_p30[23:21],g0_p29[23:21],g0_p28[23:21],g0_p27[23:21],g0_p26[23:21],g0_p25[23:21],g0_p24[23:21],
                                  g0_p23[23:21],g0_p22[23:21],g0_p21[23:21],g0_p20[23:21],g0_p19[23:21],g0_p18[23:21],g0_p17[23:21],g0_p16[23:21],
                                  g0_p15[23:21],g0_p14[23:21],g0_p13[23:21],g0_p12[23:21],g0_p11[23:21],g0_p10[23:21],g0_p9 [23:21],g0_p8 [23:21],
                                  g0_p7 [23:21],g0_p6 [23:21],g0_p5 [23:21],g0_p4 [23:21],g0_p3 [23:21],g0_p2 [23:21],g0_p1 [23:21],g0_p0 [23:21],
                                                                                                                                                
                                //g0_p31[20:18],g0_p30[20:18],g0_p29[20:18],g0_p28[20:18],g0_p27[20:18],g0_p26[20:18],g0_p25[20:18],g0_p24[20:18],
                                  g0_p23[20:18],g0_p22[20:18],g0_p21[20:18],g0_p20[20:18],g0_p19[20:18],g0_p18[20:18],g0_p17[20:18],g0_p16[20:18],
                                  g0_p15[20:18],g0_p14[20:18],g0_p13[20:18],g0_p12[20:18],g0_p11[20:18],g0_p10[20:18],g0_p9 [20:18],g0_p8 [20:18],
                                  g0_p7 [20:18],g0_p6 [20:18],g0_p5 [20:18],g0_p4 [20:18],g0_p3 [20:18],g0_p2 [20:18],g0_p1 [20:18],g0_p0 [20:18]};
        endcase
    else if(wren && reg_grp==0)
        case(wr_cnt)
            0:      ram_wdata <= {
                                //g1_p31[5 :3 ],g1_p30[5 :3 ],g1_p29[5 :3 ],g1_p28[5 :3 ],g1_p27[5 :3 ],g1_p26[5 :3 ],g1_p25[5 :3 ],g1_p24[5 :3 ],
                                  g1_p23[5 :3 ],g1_p22[5 :3 ],g1_p21[5 :3 ],g1_p20[5 :3 ],g1_p19[5 :3 ],g1_p18[5 :3 ],g1_p17[5 :3 ],g1_p16[5 :3 ],
                                  g1_p15[5 :3 ],g1_p14[5 :3 ],g1_p13[5 :3 ],g1_p12[5 :3 ],g1_p11[5 :3 ],g1_p10[5 :3 ],g1_p9 [5 :3 ],g1_p8 [5 :3 ],
                                  g1_p7 [5 :3 ],g1_p6 [5 :3 ],g1_p5 [5 :3 ],g1_p4 [5 :3 ],g1_p3 [5 :3 ],g1_p2 [5 :3 ],g1_p1 [5 :3 ],g1_p0 [5 :3 ],

                                //g1_p31[2 :0 ],g1_p30[2 :0 ],g1_p29[2 :0 ],g1_p28[2 :0 ],g1_p27[2 :0 ],g1_p26[2 :0 ],g1_p25[2 :0 ],g1_p24[2 :0 ],
                                  g1_p23[2 :0 ],g1_p22[2 :0 ],g1_p21[2 :0 ],g1_p20[2 :0 ],g1_p19[2 :0 ],g1_p18[2 :0 ],g1_p17[2 :0 ],g1_p16[2 :0 ],
                                  g1_p15[2 :0 ],g1_p14[2 :0 ],g1_p13[2 :0 ],g1_p12[2 :0 ],g1_p11[2 :0 ],g1_p10[2 :0 ],g1_p9 [2 :0 ],g1_p8 [2 :0 ],
                                  g1_p7 [2 :0 ],g1_p6 [2 :0 ],g1_p5 [2 :0 ],g1_p4 [2 :0 ],g1_p3 [2 :0 ],g1_p2 [2 :0 ],g1_p1 [2 :0 ],g1_p0 [2 :0 ]};

            1:      ram_wdata <= {
                                //g1_p31[11:9 ],g1_p30[11:9 ],g1_p29[11:9 ],g1_p28[11:9 ],g1_p27[11:9 ],g1_p26[11:9 ],g1_p25[11:9 ],g1_p24[11:9 ],
                                  g1_p23[11:9 ],g1_p22[11:9 ],g1_p21[11:9 ],g1_p20[11:9 ],g1_p19[11:9 ],g1_p18[11:9 ],g1_p17[11:9 ],g1_p16[11:9 ],
                                  g1_p15[11:9 ],g1_p14[11:9 ],g1_p13[11:9 ],g1_p12[11:9 ],g1_p11[11:9 ],g1_p10[11:9 ],g1_p9 [11:9 ],g1_p8 [11:9 ],
                                  g1_p7 [11:9 ],g1_p6 [11:9 ],g1_p5 [11:9 ],g1_p4 [11:9 ],g1_p3 [11:9 ],g1_p2 [11:9 ],g1_p1 [11:9 ],g1_p0 [11:9 ],

                                //g1_p31[8 :6 ],g1_p30[8 :6 ],g1_p29[8 :6 ],g1_p28[8 :6 ],g1_p27[8 :6 ],g1_p26[8 :6 ],g1_p25[8 :6 ],g1_p24[8 :6 ],
                                  g1_p23[8 :6 ],g1_p22[8 :6 ],g1_p21[8 :6 ],g1_p20[8 :6 ],g1_p19[8 :6 ],g1_p18[8 :6 ],g1_p17[8 :6 ],g1_p16[8 :6 ],
                                  g1_p15[8 :6 ],g1_p14[8 :6 ],g1_p13[8 :6 ],g1_p12[8 :6 ],g1_p11[8 :6 ],g1_p10[8 :6 ],g1_p9 [8 :6 ],g1_p8 [8 :6 ],
                                  g1_p7 [8 :6 ],g1_p6 [8 :6 ],g1_p5 [8 :6 ],g1_p4 [8 :6 ],g1_p3 [8 :6 ],g1_p2 [8 :6 ],g1_p1 [8 :6 ],g1_p0 [8 :6 ]};

            2:      ram_wdata <= {
                                //g1_p31[17:15],g1_p30[17:15],g1_p29[17:15],g1_p28[17:15],g1_p27[17:15],g1_p26[17:15],g1_p25[17:15],g1_p24[17:15],
                                  g1_p23[17:15],g1_p22[17:15],g1_p21[17:15],g1_p20[17:15],g1_p19[17:15],g1_p18[17:15],g1_p17[17:15],g1_p16[17:15],
                                  g1_p15[17:15],g1_p14[17:15],g1_p13[17:15],g1_p12[17:15],g1_p11[17:15],g1_p10[17:15],g1_p9 [17:15],g1_p8 [17:15],
                                  g1_p7 [17:15],g1_p6 [17:15],g1_p5 [17:15],g1_p4 [17:15],g1_p3 [17:15],g1_p2 [17:15],g1_p1 [17:15],g1_p0 [17:15],

                                //g1_p31[14:12],g1_p30[14:12],g1_p29[14:12],g1_p28[14:12],g1_p27[14:12],g1_p26[14:12],g1_p25[14:12],g1_p24[14:12],
                                  g1_p23[14:12],g1_p22[14:12],g1_p21[14:12],g1_p20[14:12],g1_p19[14:12],g1_p18[14:12],g1_p17[14:12],g1_p16[14:12],
                                  g1_p15[14:12],g1_p14[14:12],g1_p13[14:12],g1_p12[14:12],g1_p11[14:12],g1_p10[14:12],g1_p9 [14:12],g1_p8 [14:12],
                                  g1_p7 [14:12],g1_p6 [14:12],g1_p5 [14:12],g1_p4 [14:12],g1_p3 [14:12],g1_p2 [14:12],g1_p1 [14:12],g1_p0 [14:12]};

            3:      ram_wdata <= {
                                //g1_p31[23:21],g1_p30[23:21],g1_p29[23:21],g1_p28[23:21],g1_p27[23:21],g1_p26[23:21],g1_p25[23:21],g1_p24[23:21],
                                  g1_p23[23:21],g1_p22[23:21],g1_p21[23:21],g1_p20[23:21],g1_p19[23:21],g1_p18[23:21],g1_p17[23:21],g1_p16[23:21],
                                  g1_p15[23:21],g1_p14[23:21],g1_p13[23:21],g1_p12[23:21],g1_p11[23:21],g1_p10[23:21],g1_p9 [23:21],g1_p8 [23:21],
                                  g1_p7 [23:21],g1_p6 [23:21],g1_p5 [23:21],g1_p4 [23:21],g1_p3 [23:21],g1_p2 [23:21],g1_p1 [23:21],g1_p0 [23:21],

                                //g1_p31[20:18],g1_p30[20:18],g1_p29[20:18],g1_p28[20:18],g1_p27[20:18],g1_p26[20:18],g1_p25[20:18],g1_p24[20:18],
                                  g1_p23[20:18],g1_p22[20:18],g1_p21[20:18],g1_p20[20:18],g1_p19[20:18],g1_p18[20:18],g1_p17[20:18],g1_p16[20:18],
                                  g1_p15[20:18],g1_p14[20:18],g1_p13[20:18],g1_p12[20:18],g1_p11[20:18],g1_p10[20:18],g1_p9 [20:18],g1_p8 [20:18],
                                  g1_p7 [20:18],g1_p6 [20:18],g1_p5 [20:18],g1_p4 [20:18],g1_p3 [20:18],g1_p2 [20:18],g1_p1 [20:18],g1_p0 [20:18]};
        endcase
//***********************************************************
//-------------------------------------
// instance of dpram_512x144_1024x72
//-------------------------------------
dpram_512x144_1024x72 data_buf(
    .wrclock    (I_sdram_clk),
    .wren       (ram_wren   ),
    .wraddress  (ram_waddr  ),
    .data       (ram_wdata  ),

    .rdclock    (I_rclk     ),
    .rden       (I_rden     ),
    .rdaddress  (I_raddr    ),
    .q          (O_rdata    )
    );
//***********************************************************
endmodule

`default_nettype wire

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